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Jens Ejury July 13, 2006 San Jose, CA
Data Sheet High-Performance DrMOS
6mm x 6mm x 0.8mm IQFN
TDA21211- Data Sheet August - 2009
Published by Infineon Technologies AG http://www.infineon.com/DCDC
Power Management & Drive
N e v e r s t o p t h i n k i n g.
Data Sheet
Page 1 of 20
TDA21211
6x6 QFN High-Performance DrMOS Features:
* * * * * * Intel compliant DrMOS, Power MOSFET and Driver in one package For Synchronous Buck - step down voltage applications Maximum Average Current of 35A Wide input voltage range +5V to +30V Low power dissipation Extremely fast switching technology for improved performance at high switching frequencies (>1MHz) * * * * * * * * * Remote Driver Disable function Switching Modulation (SMOD#) of low side MOS Includes active PMOS structure as integrated bootstrap circuit for reduced part count Shoot through protection +5V High and Low Side Driving voltage Compatible to standard PWM controller ICs with +3.3 and 5V logic Three-State PWM input functionality Small Package: IQFN40 (6 x 6 x 0.8 mm3) RoHS Compliant * * * * * TDA21211 Type Package 6x6x0.8mm3 PG-IQFN-40-1 Marking TDA21211
Applications:
* Desktop and Server VR11.X and VR12 Vcore and non-Vcore buckconverters Network and Telecom processor VR Single Phase and MultiPhase POL CPU/GPU Regulation in Notebook, Graphics Cards, and Gaming Voltage Modules requiring high power density Memory (DDR2/3)
Data Sheet
Page 2 of 20
TDA21211
Pinout
PHASE CGND VDRV BOOT VIN GH VCIN VIN NC SMOD# 10 VIN 11 VIN 12 VIN 13 VIN 14 VSWH 15 PGND PGND PGND PGND PGND 16 17 18 19 20 21 PGND 22 PGND 23 PGND 24 PGND 25 PGND 26 PGND 27 PGND 28 PGND 29 VSWH 30 VSWH 9 8 7 6 5 4 3 2 1 40 39 PWM DISB# NC CGND GL VSWH VSWH VSWH VSWH VSWH
VIN
CGND
38 37 36 35 34
Note: Signals marked with "#" at the end are active low signals.
VSWH
33 32 31
Figure 1. Pinout, numbering and name of pins (Transparent Top View)
Pin Description
Pin Name
CGND SMOD# VCIN VDRV BOOT GH PHASE NC VIN VSWH PGND GL DISB# PWM
Pin No.
5, 37,CGND Pad 1 2 3 4 6 7 8, 38 9 to 14, Vin Pad 15, 29 to 35, VSWH Pad 16 to 28 36 39 40
Description
Control signal ground Low side gate disable pin Logic supply voltage FET gate supply voltage Bootstrap voltage pin High side gate signal Switch node output No connect Input Voltage Switch node output Power ground Low side gate signal Disable Signal (active low) PWM drive logic input
Remarks
Should be connected to PGND externally when SMOD# is "low" the GL is OFF 5V bias voltage for the internal logic. High & Low Side gate drive 5V Connect to boot capacitor pin for monitoring gate of HS FET Internally connected to VSWH pin Can be connected to any potential connection to the drain of the HS FET high current output switch node All of these pins must be connected to the power GND plane through multiple, low inductance vias. pin for monitoring gate of LS FET pull to GND to disable the IC the three-state PWM input is compatible with 3.3V and 5V logic
Data Sheet
Page 3 of 20
TDA21211
General Description
The Infineon TDA21211 is a multichip module that incorporates Infineon's premier MOSFET technology for a single high side and a single low side MOSFET coupled with a robust, high performance, high switching frequency gate driver in a single 40 pin QFN package. The optimized gate timing allows for significant light load efficiency improvements over discrete solutions. State of the art MOSFET technology provides exceptional full load performance. Thus this device has a clear advantage over exisiting approaches in the marketplace when both full load and light load efficiencies are important. The Driver+MOSFET IC TDA21211 (DrMOS) is pin to pin compatible and compliant with the Intel 6x6 DrMOS specification. The device package height is only 0.8mm, and is an excellent choice for applications with critical height limitations.
BLOCK DIAGRAM
VCIN PHASE BOOT GU
VDRV
HS Driver UVLO Level Shifter
500k
HS MOS
VIN
DISB#
500k
HS Logic
Shoot Through Protection
CGND VCIN
VSWH
33k
PWM
14k
Input Logic 3-State LS Logic
VDRV
CGND VCIN
LS MOS
400k
SMOD#
600K CGND
LS Driver
500k
IC DRIVER
PGND
CGND
VDRV
GL
Figure 2. Simplified block diagram
Data Sheet
Page 4 of 20
TDA21211
Electrical Specification Table
Absolute Maximum Ratings (Ta = 25C)
Item Frequency Average output current Input voltage Supply voltage High and Low side driver voltage Switch node voltage BOOT voltage SMOD# voltage DISB# voltage 1 PWM voltage
1
Symbol fSW Iout VIN (DC) VCIN (DC) VDRV (DC) VSWH (DC) VBOOT-PHASE (DC) VSMOD# (DC) VDISB Vpwm Tj-opr Tstg
Rating 1.2 35 -0.3 to +30 -0.3 to +5.5 -0.3 to +5.5 -1 to +30 -1 to +5.5 -0.3 to +5.5 -0.3 to +5.5 -0.3 to +5.5 -40 to +150 -55 to +150
Units MHz A V V V V V V V V C C
Operating junction temperature Storage temperature
Note: All rated voltages are relative to voltages on the CGND and PGND pins unless otherwise specified.
1
Latch Up class II- Level B (Jedec 78). Please refer to Quality Report for details.
Thermal Characteristics
Parameter Thermal resistance, junction-soldering point 1 Thermal resistance, junction-top of package Symbol Min. JS Jtop Values Typ. 5 K/W 20 Max. Unit
1
junction-soldering point is referred to the VSWH bottom exposed pad.
Data Sheet
Page 5 of 20
TDA21211
Recommended Operating Conditions and Electrical Characteristics (VCIN = 5V, Ta = 25C)
Parameter
Input Voltage Driving Voltage Bias Supply Voltage UVLO Rising UVLO Falling Driver Current
Symbol
VIN VDRV VCIN VUVLO_R VUVLO_F
Min
5
Typ
5
Max
25
Units
Test Conditions
4.5 2.9 2.5
5 3.5 3.1 10 25 250 370
5.5 3.9 3.3
V
VCIN rising VCIN falling
IVDRV_300kHz IVDRV_PWML IVCIN_PWML IVCIN_O
mA A A A 270 A
DISB# = 5V, fSW = 300kHz DISB# = 5V, PWM = 0V DISB# = 5V, PWM = 0V SMOD# = Open DISB# = 5V, PWM = Open SMOD# = Open DISB# = 0V
IC Current (Control) IC quiescent Logic Inputs and Thresholds
DISB#
ICIN+IDRV VDISB_L VDISB_H IDISB VSMOD#_L VSMOD#_H VSMOD#_O ISMOD# VPWM_L VPWM_H RIN-PWM VPWM_O VPWM_S
1.2 2.4 6.5 9.5 1.5 0.7 1.9
Input low Input high Sink Current Input low Input high Open Voltage Sink Current Input low Input high
0.7 1.9
1.1 2.1 2 1.1 2.1 3.0 -8
1.3 2.4 1.3 2.4
V A V
VDISB falling VDISB rising VDISB = 1V VSMOD# falling VSMOD# rising VSMOD# = 1V VPWM falling VPWM rising VPWM = 1V VPWM_O
SMOD#
A 0.7 12.5 1.9 V k V
PWM
Input resistance Open Voltage Tri-state Shutdown Window
Dynamic Characteristic Three State to GL/GH rising propagation delay GL/GH Three State Shutdown Hold-Off time, GH Turn-on propagation delay GH Turn-off propagation delay GL Turn-on propagation delay GL Turn-off propagation delay DISB#Turn-off propogation delay falling DISB#Turn-on propogation delay rising
1
T_pts T_tsshd T_pdhu T_pdlu T_pdhl T_pdll T_pdl_DISB T_pdh_DISB
15 240 15 20 ns 20 10 20 20 GH, GL unloaded.
Unless otherwise specified, VCIN=VDRV
Data Sheet
Page 6 of 20
TDA21211
Typical Application
VCIN
+5 V + 3.3 V
VDD VIN_SEN
VIN BOOT VCIN VDRV PHASE VSWH
VIN
+12 V
Cboot Rboot
L Rb Cb
TDA 21211
CGND PGND
PX3560 PWM1
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 PSI# OUTEN VR_READY FAULT1 FAULT2 FAULT3 SDA SCL
SEN1N PWM1 SEN1P ISEN1N
PWM
Cboot
Rboot
ISEN1P PWM2 ISEN2N ISEN2P
PWM2 SEN2N SEN2P
VIN BOOT VCIN VDRV PWM PHASE VSWH
L Rb Cb
TDA 21211
CGND PGND
PWM3
ISEN3N ISEN3P PWM4 ISEN4N ISEN4P
Cboot Rboot
VIN BOOT VCIN VDRV PWM
PHASE VSWH
L Rb Cb
TDA 21211
CGND PGND
PWM5 PWM3 ISEN5N SEN3N
SEN3P ISEN5P
Cboot
Rboot
PWM6 ISEN6N
VIN BOOT VCIN VDRV PHASE VSWH
L Rb Cb
SADDR_M SADDR_L
ISEN6P
PWM4
TDA 21211
CGND PGND
PWM
VD25
SEN4N
GND
SEN4P VSENP VSENN
VOUT COUT
VSENP
VSENN
Figure 3. Four Phases Voltage Regulator Typical Application (Simplified Schematic) Data Sheet Page 7 of 20 TDA21211
Theory of Operation
The TDA21211 incorporates a high performance gate driver, one high side power MOSFET and one low-side power MOSFET in a single 40 lead QFN package. The advantages of this arrangement are found in the areas of increased performance, increased efficiency and lower overall package and layout inductance.This module is ideal for use in Synchronous Buck Regulators either as a stand-alone power stage that can deliver up to 35A or with an interleaved approach for higher current loads. The power MOSFETs are tailored for this device. The gate driver is an extremely robust high-performance driver rated at the switching node for DC voltages ranging from -1V to +30V. The closely coupled driver and MOSFETs enable efficiency improvements that are hard to match using discrete components. The power density for transmitted power of this approach is approximately 30W within a 36mm2 area. Driver Characteristics The gate driver of the TDA21211 has 2 voltage inputs, VCIN and VDRV. VCIN is the 5V bias supply for the driver. VDRV is also 5V and is used to drive the High and Low Side MOSFETs. Ceramic capacitors should be placed very close to these input voltage pins to decouple the sensitive control circuitry from a noisy environment. The MOSFETs selected for this application are optimized for 5V gate drive, thus giving the end user optimized high load as well as light load efficiency. The reference for the power circuitry including the driver output stage is PGND and the reference for the gate driver control circuit (VCIN) is CGND. Referring to the Block Diagram, Figure 2 VCIN is internally connected to the UVLO circuit and for VCIN voltages less than required for proper circuit operation will provide shut-down. VDRV supplies both, the floating high side drive and the low-side drive circuits. An active boot circuit for the high side gate drive is also included. A second UVLO circuitry, sensing the BOOT voltage level, is implemented to prevent false GH turn on during insufficient power supply level condition (BOOT Cap charging/discharging sequence). During undervoltage both GH and GL are driven low actively; further passive pull down (500k Ohm) is placed on each gate. Note: output signal from UVLO unit.
UVLO Output Logic Level
"H"
Shutdown Enable
"L"
VUVLO_F
VUVLO_R
VCIN
Data Sheet
Page 8 of 20
TDA21211
Inputs to the internal control circuit are PWM, DISB# and SMOD#: The PWM is the control input to the IC from an external PWM controller and is compatible with 3.3V and 5V logic. The PWM input has three-state functionality. When the voltage remains in the specified PWM-shutdown-window for at least the PWM-shutdown-holdoff time T_tsshd, the operation will be suspended by keeping both MOSFET gate outputs low. Once left open, the pin is internally fixed to VPWM_O = 1.5 V level
PWM L H Open
Driver Output GL=H, GH = L GL=L, GH = H GL=L, GH = L
The DISB# is an active low signal. When DISB# is pulled low, the power stage is disabled.
DISB# L H Open
Driver Output Shutdown Enable Shutdown GL, GH = L GL, GH = L GL, GH = "Active"
The SMOD# feature is provided to disable the low-side MOSFET during active operation. When synchronized with the PWM signal (as shown in Figure 7), SMOD# is intended to improve light load efficiency by saving the gate charge loss of the low-side MOSFET. Once left open, the pin is internally fixed to VSMOD#_O = 3 V level.
SMOD# L H Open
GL Status L Enable Enable GL= "Active" GL= "Active"
The TDA21211 driver includes gate drive functionality to protect against shoot through. In order to protect the power stage from overlap, both HS and LS MOSFETs being on at the same time, the adaptive control circuitry monitors the voltage at the "VSWH" pin. When the PWM signal goes low, HS, the High-side MOSFET will begin to turn off, after the propagation delay (T_pdlu). Once the "VSWH" pin falls below 1V, LS, the Low-side MOSFET is gated on after the predefined delay time, (T_pdhl). Additionally, the gate to source voltage of the HS-MOSFET is also monitored. When VGS(HS) is discharged below 1V, a threshold known to turn HS off, a secondary delay is initiated, (T_pdhl), which results in LS being gated "ON" irregardless of the state of the "VSWH" pin.This way it will be ensured that the converter can sink current efficiently and the bootstrap capacitor will be refreshed appropriately during each switching cycle. See Figure 5 for more detail. GH and GL are monitoring pins to check the internal gate drive signals.
Data Sheet
Page 9 of 20
TDA21211
CBOOT
0.1 / 1u F
+5v
1u F
RBOOT
0/5 CGND
GH VCIN
CGND
SMOD BOOT VDRV
VIN
VIN (+ 5 / 24 v) CIN 4x10u F
11 12 10 9
PHASE
NC
CGND
8
7
6
5
4
3
2
1 PWM 40 DISB# 39
VIN
13 14
VIN
CGND
38 NC 37 36 35 34
CGND GL VSWH
VSWH PGND
15 16 17 18 19 20
VSWH
33 32 31
Signal GND
Power GND
21 22 23 24 25 26 27 28 29 30
L
VOUT
PGND
Figure 4. Pin interconnection outline (Transparent Top View) NOTE: RBOOT value is related to the input voltage level. Pin PHASE is internally connected to VSWH node.
Data Sheet
Page 10 of 20
VSWH
TDA21211
Gate Driver Timing Diagrams
VPWM_H VPWM_H VPWM_L
PWM T_pdll T_tsshd T_pts GL T_pdhl 1V Three State
VPWM_L
T_tsshd T_pdlu T_pts T_pdhu
GH
1V VSWH
Note: VSWH during entering/exit to tristate behaves accordingly to inductor current.
Figure 5: Adaptive Gate Driver Timing Diagram
Data Sheet
Page 11 of 20
TDA21211
DISBL#
VDISB_H
VDISB_L
T_pdl(DISB)
T_pdh(DISB)
GH/GL
Figure 6: Disable Timing Diagram
SMOD SMOD disabled
SMOD active
PWM
GL T_pdlu T_pdlu T_pdlu
VSWH
CCM
DCM
CCM
Figure 7 SMOD# Timing Diagram Page 12 of 20
Data Sheet
TDA21211
Test Circuit
VIN IIN A V VCIN ICIN A V IDRV A V CDRV CCIN CIN
VDRV
VDRV PWM PWM
VIN BOOT
CBOOT
PHASE
VCIN DISBL#
TDA21211
VSWH
L 300n H Rb
PGND
VOUT IOUT Cb
PX3560
SMOD# CGND
ISENN ISENP VSENP VSENN
COUT
Figure 8. Test Circuit
Efficiency =
POUT PIN
PIN = VDRV x I DRV + VCIN x I CIN + VIN x I IN POUT = VOUT x I OUT PLOSS = PIN - POUT
Data Sheet
Page 13 of 20
TDA21211
Performance Curves - Typical Data
Operating conditions (unless otherwise specified): VIN= +12V, VCIN=VDRV= +5V, VOUT=1.1 V, F=362k Hz, 300nH inductor (VITEC59P9081N01, DCR (typ) =0.43m ) TA=25 C, load line=0m, airflow=100 LFM, no heatsink. Power Efficiency and Power Loss data reported herein includes TDA21211 and inductor losses but no other system losses (unless otherwise specified).
94 92 90 Efficiency (%) 88 86 84 82 80 0 5 10 15 20 Output Current (A) 25
1.6V 1.5V 1.2V 1.0V 0.8V
7
0.8V
6 5 Power Loss (W) 4 3 2 1 0
1.0V 1.2V 1.5V 1.6V
30
0
5
10 15 20 Output Current (A)
25
30
Figure 9. Efficiency vs. VOUT
Figure 10. Power Loss vs. VOUT
94 92 90 Efficiency (%) 88 86 84 82 80 0 5 10 15 20 25
296Khz 362Khz 407Khz 465Khz 592Khz
7 6 5 Power Loss (W) 4 3 2 1 0
592Khz 465Khz 407Khz 362Khz 296Khz
30
0
5
Output Current (A)
10 15 20 Output Current (A)
25
30
Figure 11. Efficiency vs. Switching Frequency
Figure 12. Power Loss vs. Switching Frequency
Data Sheet
Page 14 of 20
TDA21211
94 92 90 Efficiency (%) 88 86 84 82 80 0 5 10 15 20 Output Current (A) 25 30
10V 12V 14V 16V 18V 20V
7
20V
6 5 Power Loss (W) 4 3 2 1 0 0 5
18V 16V 14V 12V 10V
10 15 20 Output Current (A)
25
30
Figure 13. Efficiency vs. VIN
Figure 14. Power Loss vs. VIN
94
25C
7
105C
65C 85C 105C
92 90 88 86 84 82 80 0 5 10 15 20 Output Current (A) 25
6 5 Power Loss (W) 4 3 2 1 0
30
85C 65C 25C
Efficiency (%)
0
5
10 15 20 Output Current (A)
25
30
Figure 15. Efficiency vs. TCASE
Figure 16. Power Loss vs. TCASE
Data Sheet
Page 15 of 20
TDA21211
7
1,20
Vin=12V
6
Vin=12V
1,15
VCIN=VDRV=5V Vout=1.3V
VCIN=VDRV=5V Vout=1.3V
5 Power Loss (W)
F=600kHz L=510nH
1,10
Iout=25A L=510nH
4
T= 25 C
1,05
T= 25 C
3
1,00
2
0,95
1
0,90
0 0 5 10 15 20 25 30
0,85 300
400
500
600
700
800
900
1000
Output Current (A) Figure 17. Power Loss vs. Iout
(inductor losses not included)
Switching Frequency (kHz) Figure 18. Normalized Power Loss @ Iout=25 A
(inductor losses not included)
35
Vin=12V
30 25 IDRV + ICIN (mA) 20 15 10 5 0 100
VCIN=VDRV=5V Vout=1.3V Iout=25A L=510nH T= 25 C
200
300
400
500
600
700
800
900
1000
Switching Frequency (kHz) Figure 19. Power Supply Current (IDRV + ICIN) vs. Fsw
Data Sheet
Page 16 of 20
TDA21211
Package Outline
PIN#1 IDENT
Data Sheet
Page 17 of 20
TDA21211
Figure 20: Footprint and Solder Stencil Recommendation
Data Sheet
Page 18 of 20
TDA21211
PCB Layout Example.
Figure 21 Single Phase DrMOS typical Application Circuit
Figure 22 Single Phase DrMOS PCB Layout Example (Top Side View) (for DrMOS Design support a customer PCB layout guide is available upon request)
Data Sheet
Page 19 of 20
TDA21211
For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see the address list on the last page or our webpage at
http://www.infineon.com/DCDC
CoreControlTM, OptiMOSTM and OptiMOS IITM are trademarks of Infineon Technologies AG.
We listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continously improve the quality of this document.
Edition 2004-11-10
Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen
(c) Infineon Technologies AG 2004. All Rights Reserved.
Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Data Sheet
Page 20 of 20
TDA21211

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